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KAD5512P-50 preliminary 300 unicorn park dr., woburn, ma 01801 sales: 1-781-497-0060 sales@kenetinc.com femtocharge is a registered trademark of kenet, inc. copyright ? 2007, kenet, inc. rev 0.5.1 preliminary page 1 general description the KAD5512P-50 is a low-power, high-performance, 12-bit, 500msps analog-to-digital converter designed with kenet?s proprietary femtocharge ? technology on a standard cmos process. the KAD5512P-50 is part of a pin-compatible portfolio of 10, 12 and 14-bit a/ds with sample rates ranging from 125msps to 500msps. the device utilizes two time-interleaved 12-bit, 250msps a/d cores to achieve the ultimate sample rate of 500msps. a single 500mhz conversion clock is presented to the converter, and all interleave clocking is managed internally. a serial peripheral interface (spi) port allows for extensive configurability, as well as fine control of matching characteristics (gain, offset, skew) between the two converter cores. these adjustments allow the user to minimize spurs associated with the interleaving process. digital output data is presented in selectable lvds or cmos formats. the KAD5512P-50 is available in a 72-contact qfn package with an exposed paddle. performance is specified over the full industrial temperature range (-40 to +85c). features ? programmable gain, offset and skew control ? 1.3 ghz analog input bandwidth ? 52fs clock jitter ? over-range indicator ? selectable clock divider: 1 or 2 ? clock phase selection ? nap and sleep modes ? two?s complement, gray code or binary data format ? ddr lvds-compatible or lvcmos outputs ? programmable built-in test patterns ? 1.8v analog and digital supplies applications ? radar and satellite antenna array processing ? broadband communications ? high-performance data acquisition 12-bit, 500msps a/d converter key specifications ? snr = 64.3dbfs for f in = 250mhz (-1dbfs) ? sfdr = 80dbc for f in = 250mhz (-1dbfs) ? power consumption = 400mw pin-compatible family model resolution speed (msps) kad5514p-25 14 250 kad5514p-21 14 210 kad5514p-17 14 170 kad5514p-12 14 125 KAD5512P-50 12 500 kad5512p-12, kad5512hp-12 12 125 kad5510p-50 10 500 kad5512p-17, kad5512hp-17 12 170 kad5512p-21, kad5512hp-21 12 210 kad5512p-25, kad5512hp-25 12 250 1.25 v vinp vinn clkp clkn vref clkoutp clkoutn d[11:0]p d[11:0]n orp orn outfmt outmode vcm vref
KAD5512P-50 rev 0.5.1 preliminary page 2 table of contents section pages electrical specifications 3?7 dc specifications 3 ac specifications 4 digital specifications 5 timing diagrams 5 switching specifications 6 absolute maximum ratings 6 thermal impedance 7 esd 7 pinout/package information 8?9 pin descriptions 8 pin configuration 9 typical performance characteristics 10?13 theory of operation 14?18 functional description 14 power-on calibration 14 user-initiated reset 15 analog input 15 clock input 16 jitter 16 voltage reference 17 digital outputs 17 power dissipation 17 nap/sleep 17 data format 18 section serial peripheral interface spi physical interface spi configuration dut information indexed dut configuration/control global dut configuration/control dut test spi memory map equivalent circuits layout considerations definitions outline dimensions ordering guide revision history pages 18?24 19 20 21 21 22 23 24 25 25 26 27 28 28
KAD5512P-50 rev 0.5.1 preliminary page 3 electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40 c to +85 c, a in = -1dbfs, f sample = 500msps. dc specifications KAD5512P-50 parameter symbol conditions min typ max units analog input full-scale analog input range v fs differential 1.38 1.45 1.59 v pp input resistance r in differential 500 ? input capacitance c in differential 4 pf full scale range temp. drift a vtc full temp 90 ppm/c input offset voltage v os 1.5 mv common-mode output voltage v cm 0.535 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 v 1.8v analog supply current i avdd 157 ma 1.8v digital supply current i ovdd 65 ma power supply rejection ratio psrr -53 dbfs power dissipation normal mode p d 400 mw nap mode p d 40 mw sleep mode p d 10 mw gain error e g 0.6 %
KAD5512P-50 rev 0.5.1 preliminary page 4 ac specifications 1. sfdr, sinad and enob specifications apply after gain error and timing skew between adc cores have been minimized through external calibration. KAD5512P-50 parameter symbol conditions min typ max units differential nonlinearity dnl f in = 10mhz -1.0 0.5 1.25 lsb integral nonlinearity inl f in = 10mhz -2.5 0.5 2.5 lsb signal-to-noise ratio snr f in = 10mhz 64.3 dbfs f in = 70mhz 64.3 dbfs f in = 974mhz 58.0 dbfs signal-to-noise and distortion 1 sinad f in = 10mhz 63.1 dbfs f in = 70mhz 63.1 dbfs f in = 974mhz 51.9 dbfs effective number of bits 1 enob f in = 10mhz 10.2 bits f in = 70mhz 10.2 bits f in = 974mhz 8.3 bits spurious-free dynamic range 1 sfdr f in = 10mhz 81 dbc f in = 70mhz 81 dbc f in = 974mhz 55 dbc word error rate 10 -12 full power bandwidth fpbw 1.3 ghz f in = 170mhz tbd dbc f in = 124mhz tbd tbd dbc two-tone sfdr 2tsfdr f in = 10mhz tbd dbc intermodulation distortion imd f in = 10mhz tbd dbc f in = 70mhz -90.5 tbd dbc f in = 170mhz -86.0 dbc f in = 140mhz tbd 64.2 dbfs f in = 230mhz 64.0 dbfs f in = 400mhz 63.2 dbfs f in = 140mhz tbd 63.0 dbfs f in = 230mhz 62.8 dbfs f in = 400mhz 61.3 dbfs f in = 140mhz tbd 10.2 bits f in = 230mhz 10.1 bits f in = 400mhz 9.9 bits f in = 140mhz tbd 79 dbc f in = 230mhz 79 dbc f in = 400mhz 70 dbc minimum conversion rate f s min tbd msps maximum conversion rate f s max 500 msps
KAD5512P-50 rev 0.5.1 preliminary page 5 digital specifications parameter symbol conditions min typ max units inputs input current high (resetn) i ih vin = 1.8v 0 1 10 a input current low (resetn) i il vin = 0v 25 50 75 a input current high (outmode, nap/slp, clkdiv, outfmt ) i ih tbd 25 tbd a input current low (outmode, nap/slp, clkdiv, outfmt ) i il tbd 25 tbd a input capacitance c di 3 pf lvds outputs differential output voltage v t 210 mv output rise time t r 500 ps output fall time t f 500 ps cmos outputs voltage output high v oh ovdd-0.1 v voltage output low v ol 0.1 v output offset voltage v os tbd mv output rise time t r tbd ns output fall time t f tbd ns timing diagrams figure 1. lvds timing diagram figure 2. cmos timing diagram
KAD5512P-50 rev 0.5.1 preliminary page 6 switching specifications absolute maximum ratings 1 1. exposing the device to levels in excess of the ma ximum ratings may cause permanent damage. exposure to maximum conditions for extended periods may affect device reliability. parameter symbol min typ max units adc aperture delay t a 375 ps rms aperture jitter j a 52 fs input clock to output clock propagation delay t cpd tbd tbd tbd ps input clock to data propagation delay t pd tbd tbd tbd ps output clock to data propagation delay t dc tbd tbd tbd ps latency (pipeline delay) l 15 cycles over voltage recovery t ovr 1 cycles parameter min max unit avdd to avss -0.4 2.1 v ovdd to ovss -0.4 2.1 v analog inputs to avss -0.4 avdd + 0.3 v clock inputs to avss -0.4 avdd + 0.3 v logic input to avss -0.4 ovdd + 0.3 v logic inputs to ovss -0.4 ovdd + 0.3 v operating temperature -40 85 c storage temperature -65 150 c junction temperature 150 c avss to ovss -0.3 0.3 v
KAD5512P-50 rev 0.5.1 preliminary page 7 thermal impedance 2. paddle soldered to ground plane. esd electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, ba lls, exposed paddle, etc.) of an integrated circuit. industry-standard protection techniques have been utilized in the design of this prod- uct. however, reasonable care must be taken in the storage and handling of esd sensitive products. contact kenet for the specific esd sensitivity rating of this product. parameter symbol typ unit junction to paddle 2 jp 30 c/w junction to case 2 jc tbd c/w junction to ambient 2 ja tbd c/w
KAD5512P-50 rev 0.5.1 preliminary page 8 pin descriptions lvcmos output mode functionality is shown in brackets (nc = no connection) pin # lvds [lvcmos] name lvds [lvcmos] function 1, 6, 12, 19, 24, 71 avdd 1.8v analog supply 2-5, 13, 14, 17, 18, 28-31 dnc do not connect 7, 8, 11, 72 avss analog ground 9, 10 vinn, vinp analog input negative, positive 15 vcm common mode output 16 clkdiv clock divider control 20, 21 clkp, clkn clock input true, complement 22 outmode output mode (lvds, lvcmos) 23 napslp power control (nap, sleep modes) 25 resetn power on reset (active low) 26, 45, 55, 65 ovss output ground 27, 36, 56 ovdd 1.8v output supply 37, 38 d2n, d2p [nc, d2] lvds bit 2 output complement, true [nc, lvcmos bit 2] 39, 40 d3n, d3p [nc, d3] lvds bit 3 output complement, true [nc, lvcmos bit 3] 41, 42 d4n, d4p [nc, d4] lvds bit 4 output complement, true [nc, lvcmos bit 4] 43, 44 d5n, d5p [nc, d5] lvds bit 5 output complement, true [nc, lvcmos bit 5] 46 rlvds lvds bias resistor (connect to ovss with a 10k ? , 1% resistor) 47, 48 clkoutn, clkoutp [nc, clkout] lvds clock output complement, true [nc, lvcmos clkout] 49, 50 d6n, d6p [nc, d6] lvds bit 6 output complement, true [nc, lvcmos bit 6] 51, 52 d7n, d7p [nc, d7] lvds bit 7 output complement, true [nc, lvcmos bit 7] 53, 54 d8n, d8p [nc, d8] lvds bit 8 output complement, true [nc, lvcmos bit 8] 57, 58 d9n, d9p [nc, d9] lvds bit 9 output complement, true [nc, lvcmos bit 9] 59, 60 d10n, d10p [nc, d10] lvds bit 10 output complement, true [nc, lvcmos bit 10] 61, 62 d11n, d11p [nc, d11] lvds bit 11 (msb) output complement, true [nc, lvcmos bit 11] 63, 64 orn, orp [nc, or] lvds over range complement, true [nc, lvcmos over range] 66 sdo spi serial data output (4.7k ? pull-up to ovdd is required) 67 csb spi chip select (active low) 68 sclk spi clock 69 sdio spi serial data input/output 70 outfmt output data format (two?s comp., gray code, offset binary) exposed paddle avss analog ground 32, 33 d0n, d0p [nc, d0] lvds bit 0 (lsb) output complement, true [nc, lvcmos bit 0] 34, 35 d1n, d1p [nc, d1] lvds bit 1 output complement, true [nc, lvcmos bit 1]
KAD5512P-50 rev 0.5.1 preliminary page 9 pin configuration figure 3. pin configuration kad5512-50 top view not to scale avdd dnc dnc dnc dnc avdd avss avss vinn vinp avss avdd dnc dnc vcm clkdiv dnc dnc avdd clkp clkn outmode napslp avdd resetn ovss ovdd dnc dnc dnc dnc d0n d0p d1n d1p ovdd d6p d6n clkoutp clkoutn rlvds ovss d5p d5n d4p d4n d3p d3n d2p d2n avss avdd outfmt sdio sclk csb sdo ovss orp orn d11p d11n d10p d10n d9p d9n ovdd ovss d8p d8n d7p d7n 72 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 50 49 48 47 46 45 44 43 42 41 40 39 38 37 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
KAD5512P-50 rev 0.5.1 page 10 typical performance curves all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = +25 c, a in = -1dbfs, f sample = 500msps. figure 4. snr & sfdr vs. f in figure 5. hd2 & hd3 vs. f in figure 6. snr & sfdr vs. a in figure 7. hd2 & hd3 vs. a in figure 8. snr & sfdr vs. f sample figure 9. hd2 & hd3 vs. f sample tbd 50 55 60 65 70 75 80 85 90 0 200 400 600 800 1000 input frequency (mhz) snrfs (dbfs) & sfdr (dbc) snr sfdr tbd tbd tbd tbd note: sfdr, sinad and enob specifications apply after gain error and timing skew between adc cores have been minimized through external calibration.
KAD5512P-50 rev 0.5.1 page 11 typical performance curves figure 10. power vs. f sample figure 11. differential nonlinearity figure 12. integral nonlinearity figure 13. snr & sfdr vs. vcm figure 14. noise histogram figure 15. single tone spectrum @ 10 mhz tbd tbd tbd tbd tbd tbd
KAD5512P-50 rev 0.5.1 page 12 typical performance curves figure 16. single tone spectrum @ 70 mhz figure 17. single tone spectrum @ 140 mhz figure 18. single tone spectrum @ 240 mhz figure 19. single tone spectrum @ 500 mhz figure 20. two-tone spectrum @ 10 mhz figure 21. two-tone spectrum @ 70 mhz tbd tbd tbd tbd tbd tbd
KAD5512P-50 rev 0.5.1 page 13 typical performance curves figure 22. two-tone spectrum @ 140 mhz figure 23. two-tone spectrum @ 240 mhz figure 24. two-tone spectrum @ 500 mhz figure 25. snr & sfdr vs. temperature figure 26. snr & sfdr vs. power supply voltage tbd tbd tbd tbd tbd
KAD5512P-50 rev 0.5.1 preliminary page 14 functional description the KAD5512P-50 is based upon a 12-bit, 250msps a/d converter core that utilizes a pipelined succes- sive approximation architecture (figure 27). the input voltage is captured by a sample-hold amplifier (sha) and converted to a unit of charge. proprietary charge domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive approximation operations determine the digital code for each input value. the converter pipeline requires twelve samples to produce a result. digital error correction is also ap- plied, resulting in a total latency of fifteen clock cy- cles. this is evident to the user as a latency between the start of a conversion and the data being avail- able on the digital outputs. the device contains two a/d converter cores with carefully matched transfer characteristics. the cores are clocked on opposite clock edges, resulting in a doubling of the sample rate. the gain, offset and skew errors between the two cores are adjustable via the spi port to minimize spurs associated with the in- terleaving process. at start-up, each core performs a self-calibration to minimize gain and offset errors. the reset pin (resetn) is initially set high at power-up and will remain in that state until the calibration is complete. the clock fre- quency should remain fixed during this time, and no spi communications should be attempted. recalibra- tion can be initiated via the spi port at any time after the initial self-calibration. power-on calibration at start-up, the core performs a self-calibration to minimize gain and offset e rrors. an internal power-on- reset (por) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins (especially 3, 4 and 18) must not be pulled up or down ? sdo (pin 66) must be high ? resetn (pin 25) must begin low ? spi communications must not be attempted a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. the sdo pin requires an external 4.7k ? pull-up to ovdd. if the sdo pin is pulled low externally during power-up, calibration will not be executed properly. figure 27. adc core block diagram
KAD5512P-50 rev 0.5.1 preliminary page 15 after the power supply has stabilized the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. the resetn pin should be connected to an open-drain driver with a drive strength of less than 0.5ma. the calibration sequence is initiated on the rising edge of resetn, as shown in figure 28. the over- range output (or) is set hi gh once resetn is pulled low, and remains in that state until calibration is com- plete. the or output returns to normal operation at that time, so it?s important that the analog input be within the converter?s full-scale range in order to ob- serve the transition. if the input is in an over-range condition the or pin will st ay high and it will not be possible to detect the end of the calibration cycle. while resetn is low, the output clock (clkoutp/clkoutn) stops toggling and is set low. normal operation of the output clock resumes at the next input clock edge (clkp/clkn) after resetn is deasserted. at 500msps the nominal calibration time is tbdms. figure 28. calibration timing user initiated reset recalibration of the adc can be initiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strength of less than 0.5ma is recommended. as is the case during power-on reset, the sdo, resetn and dnc pins must be in the proper state for the calibra- tion to successfully execute. analog input each adc core contains a fully differential input (ainp/ainn, binp/binn) to the sample and hold am- plifier (sha). the ideal full-scale input voltage is 1.45v, centered at the vcm voltage of 0.535v as shown in figure 29. figure 29. analog input range best performance is obtained when the analog in- puts are driven differentially. the common mode out- put voltage, vcm, should be used to properly bias the inputs as shown in figures 30 through 32. an rf transformer will give the best noise and distortion per- formance for wideband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in figures 30 and 31. figure 30. transformer input for general purpose applications figure 31. transmission-line transformer input for high if applications a back-to-back transformer scheme is used to im- prove common mode rejection, which keeps the common mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differen- tial input resistance of the kad5512p is 500 ? . the sha design uses a switched capacitor input stage, which creates charge kick-back when the sampling capacitance is reconnected to the input voltage. this kick-back creates a disturbance at the input which must settle before the next sampling point. lower source impedance will result in faster
KAD5512P-50 rev 0.5.1 preliminary page 16 settling and improved performance. therefore a 1:1 transformer and low shunt resistance are recom- mended for optimal performance. figure 32. differential amplifier input a differential amplifier, as shown in figure 32, can be used in applications that re quire dc-coupling. in this configuration the amplifier will typically dominate the achievable snr and distortion performance. clock input the clock input circuit is a differential pair (see figure 47). driving these inputs with a high level (up to 1.8v pp on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 im- pedance ratio will provide increased drive levels. the recommended drive circui t is shown in figure 33. the clock can be driven single-ended, but this will reduce the edge rate an d may impact snr perform- ance. the clock inputs are internally self-biased to avdd/2 to facilitate ac coupling. figure 33. recommended clock drive a selectable 2x divider is provided in series with the clock input. the divider can be used in the 2x mode with a sample clock equal to twice the desired sam- ple rate. this will result in a clock input with 50% duty cycle and will maximize the converter?s perform- ance. table 1. clkdiv pin settings the clock divider can also be controlled through the spi port, which overrides the clkdiv pin setting. de- tails on this are contained in the serial peripheral in- terface section. jitter in a sampled data system, clock jitter directly im- pacts the achievable snr performance. the theoreti- cal relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 34. equation 1. figure 34. snr vs. clock jitter this relationship shows the snr that would be achieved if clock jitter were the only non-ideal fac- tor. in reality, achievable snr is limited by internal factors such as linearity, aperture jitter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in fi gure 1. the internal aper- ture jitter combines with the input clock jitter in a root- sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. clkdiv pin divide ratio avss 2 float 1 avdd not allowed ? ? ? ? ? ? ? ? = j in t f snr 2 1 log 20 10 tj=100ps tj=10ps tj=1ps tj=0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 input frequency - mhz snr - db
KAD5512P-50 rev 0.5.1 preliminary page 17 voltage reference a temperature compensated voltage reference pro- vides the reference charges used in the successive approximation operations. the full-scale range of each a/d is proportional to the reference voltage. the nominal value of the voltage reference is 1.25v. digital outputs output data is available as a parallel bus in lvds- compatible or cmos modes. in either case, the data is presented in double data rate (ddr) format. fig- ures 1 and 2 show the timing relationships for lvds and cmos modes, respectively. additionally, the drive current for lvds mode can be set to a nominal 3 ma or a power-saving 2 ma. the lower current setting can be used in designs where the receiver is in close physical proximity to the adc. the applicability of this setting is dependent upon the pcb layout, therefore the user should experiment to determine if performance degradation is observed. the output mode and lvds drive current are se- lected via the outmode pin as shown in table 2. table 2. outmode pin settings the output mode can also be controlled through the spi port, which overrides the outmode pin setting. details on this are contained in the serial peripheral interface section. an external resistor creates the bias for the lvds driv- ers. a 10k ? , 1% resistor must be connected from the rlvds pin to ovss. power dissipation the power dissipated by the kad5512p is primarily dependent on the sample rate, but is also related to the input signal in cmos output mode. there is a static bias in the analog supply, while the remaining power dissipation is linear ly related to the sample rate. the output supply dissipation is approximately constant in lvds mode, but linearly related to the clock frequency in cmos mode. figures 35 and 36 illustrate these relationships. figure 35. power vs. sample rate, lvds mode figure 36. power vs. sample rate, cmos mode nap/sleep portions of the device may be shut down to save power during times when operation of the adc is not required. two power saving modes are available: nap, and sleep. nap mode reduces power dissipa- tion to 40mw and recovers to normal operation in approximately 1 s. sleep mode reduces power dissi- pation to 10mw but requires 1ms to recover. the clock should remain running and at a fixed fre- quency during nap or sleep. recovery time from nap mode will increase if the clock is stopped, since the internal dll can take up to 52 s to regain lock at 500msps. by default after the device is powered on, the opera- tional state is controlled by the napslp pin as shown in table 3. table 3. napslp pin settings outmode pin mode avss lvcmos float lvds, 3 ma avdd lvds, 2 ma tbd tbd napslp pin mode avss normal float sleep avdd nap
KAD5512P-50 rev 0.5.1 preliminary page 18 the power down mode can also be controlled through the spi port, which overrides the napslp pin setting. details on this are contained in the serial pe- ripheral interface section. this is an indexed function when controlled from the spi, but a global function when driven from the pin. data format output data can be presented in three formats: two?s complement, gray code and offset binary. the data format is selected vi a the outfmt pin as shown in table 4. table 4. outfmt pin settings the data format can also be controlled through the spi port, which overrides the outfmt pin setting. de- tails on this are contained in the serial peripheral in- terface section. offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most posi- tive input to 0xfff (all ones). two?s complement cod- ing simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 37 shows this operation. figure 37. binary to gray code conversion converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 38. figure 38. gray code to binary conversion mapping of the input voltage to the various data for- mats is shown in table 5. table 5. input voltage to output code mapping serial peripheral interface a serial peripheral interface (spi) bus is used to facili- tate configuration of the device and to optimize per- formance. the spi bus consists of chip select (csb), serial clock (sclk) and se rial data input/output (sdio). the maximum sclk rate is equal to the adc sample rate (f sample ) divided by 16 for write opera- tions and f sample divided by 66 for reads. at f sample = 250mhz, maximum sclk is 15.63mhz for writing and 3.79mhz for write operations. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust performance outfmt pin mode avss offset binary float two?s complement avdd gray code input voltage gray code ?full scale 000000000000 ?full scale + 1lsb 000000000001 +full scale 100000000000 offset binary 000000000000 000000000001 111111111111 two?s complement 100000000000 100000000001 011111111111 mid?scale 100000000000 000000000000 110000000000 +full scale ? 1lsb 111111111110 011111111110 100000000001
KAD5512P-50 rev 0.5.1 preliminary page 19 or functional parameters. ma ny registers in the avail- able address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined val- ues within defined registers are reserved and should not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the spi port operates in a half or full duplex mas- ter/slave configuration, with the KAD5512P-50 func- tioning as a slave. multiple slave devices can inter- face to a single master. the chip-select bar (csb) pin determines when a slave device is being addressed. multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time. if multiple slave devices are selected for reading at the same time, the results will be indeter- minate. the serial clock pin (sclk) provides synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin. the state of the sdio pin is set automatically in the communi- cation protocol (described below). a dedicated se- rial data output pin (sdo) can be activated by set- ting 0x00[7] high to allow operation in full duplex mode. the communication protocol begins with an instruc- tion/address phase. the first rising sclk edge follow- ing a high to low transition on csb determines the beginning of the two-byte instruction/address com- mand. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figures 39 and 40 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode the address is incremented for multi-byte transfers, while in lsb-first mode it?s decremented. in the default mode the msb is r/w, which deter- mines if the data is to be read (active high) or writ- ten. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see ta- ble 6). the lower 13 bits contain the first address for the data transfer. this relati onship is illustrated in fig- ure 41, and timing values are given in the switching specifications section. after the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the adc (based on the r/w bit status). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is al- lowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. for transfers of four bytes or more, csb is al- lowed stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point the state machine will reset and terminate the data transfer. figure 39. msb-first addressing figure 40. lsb-first addressing
KAD5512P-50 rev 0.5.1 preliminary page 20 table 6. byte transfer selection figures 42 and 43 illustrate the timing relationships for 2-byte and n-byte transfers, respectively. the opera- tion for a 3-byte transfer can be inferred from these diagrams. spi configuration address 0x00: chip_port_config bit ordering and spi reset are controlled by this regis- ter. bit order can be selected as msb to lsb (msb first) or lsb to msb (lsb first) to accommodate various mi- crocontrollers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to inter- pret serial data as arriving in lsb to msb order. bit 5 soft reset [w1:w0] bytes transferred 00 1 01 2 10 3 11 4 or more figure 43. n-byte transfer figure 42. 2-byte transfer figure 41. instruction/address phase
KAD5512P-50 rev 0.5.1 preliminary page 21 setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. address 0x02: burst_end if a series of sequential registers are to be set, burst mode can improve throughput by eliminating redun- dant addressing. in 3-wire spi mode the burst is ended by pulling the csb pi n high. if the device is operated in 2-wire mode the csb pin is not available. in that case, setting the burst_end address deter- mines the end of the transfer. during a write opera- tion, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. bits 7:0 burst end address this register value determines the ending ad- dress of the burst data. dut information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, re- spectively, can be read from these two registers. indexed dut configuration/control address 0x10: device_index_a bits 1:0 adc01, adc00 determines which adc is addressed. valid states for this register are 0x01 or 0x10. the two adc cores cannot be ad justed concurrently. a common spi map, which can accommodate sin- gle-channel or multi-channel devices, is used for all kenet adc products. certain configuration com- mands (identified as indexed in the spi map) can be executed on a per-converter basis. this register de- termines which converter is being addressed for an indexed command. it is impo rtant to note that only a single converter can be addressed at a time. this register defaults to 00h, indicating that no adc is addressed. address 0x20: offset_coarse address 0x21: offset_fine the input offset of the adc core can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 7. the data for- mat is twos complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incre- mented or decremented value back to the same register. table 7. offset adjustments address 0x22: gain_coarse address 0x23: gain_medium address 0x24: gain_fine gain of the adc core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjust- ment while medium and fine are 8-bit. the data for- mat is twos complement for all three registers. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incre- mented or decremented value back to the same register. table 8. coarse gain adjustment parameter 0x20[7:0] coarse offset 0x21[7:0] fine offset steps 256 256 ?full scale (0x80) -24.0mv -1.7mv +full scale (0x7f) +23.8mv +1.7mv nominal step size 187.5 v 13.3 v mid?scale (0x00) 0.0mv 0.0mv parameter 0x22[3:0] coarse gain steps 16 ?full scale (0x08) -11.2% mid?scale (0x00) 0.0% +full scale (0x07) +9.8% nominal step size 1.4%
KAD5512P-50 rev 0.5.1 page 22 table 9. medium and fine gain adjustments address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level napslp pin can select normal operation, nap or sleep modes (refer to nap/sleep section). this functionality can be overridden and controlled through the spi. this is an indexed function when controlled from the spi, but a global function when driven from the pin. this register is not changed by a soft reset. table 10. power down control global dut configuration/control address 0x70: skew_diff the value in the skew_diff register adjusts the timing skew between the two adcs cores. the nominal range and resolution of this adjustment are given in table 11. the default value of this register after power-up is 00h. table 11. differential skew adjustment address 0x71: phase_slip when using a clock divider, it?s not possible to deter- mine the synchronization of the incoming and di- vided clock phases. this is particularly important when multiple adcs are used in a time-interleaved system. the phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle, as sh own in figure 44. figure 44. phase slip address 0x72: clock_divide the kad5512p has a selectable clock divider that can be set to divide by four, two or one (no division). by default, the tri-level clkdiv pin selects the divisor (refer to clock input section). this functionality can be overridden and controlled through the spi, as shown in table 12. this regi ster is not changed by a soft reset. table 12. clock divider selection address 0x73: output_mode_a the output_mode_a register controls the physical output format of the data, as well as the logical cod- ing. the kad5512p can present output data in two physical formats: lvds or lvcmos. additionally, the drive strength in lvds mode can be set high (3ma) or low (2ma). by default, the tri-level outmode pin se- lects the mode and drive level (refer to digital out- puts section). this functionality can be overridden and controlled through the spi, as shown in table 13. data can be coded in three possible formats: two?s complement, gray code or offset binary. by default, the tri-level outfmt pin selects the data format (refer to data format section). this functionality can be parameter 0x23[7:0] medium gain 0x24[7:0] fine gain steps 256 256 ?full scale (0x80) -10.56% -1.06% mid?scale (0x00) 0.0% 0.0% +full scale (0x7f) +10.48% +1.05% nominal step size 0.0825% 0.00825% value 0x25[2:0] power down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode parameter 0x70[7:0] differential skew steps 256 ?full scale (0x08) -6.5ps mid?scale (0x00) 0.0ps +full scale (0x07) +6.5ps nominal step size 51fs value 0x72[2:0] clock divider 000 pin control 001 divide by 1 010 divide by 2 100 divide by 4
KAD5512P-50 rev 0.5.1 page 23 overridden and controlled through the spi, as shown in table 14. this register is not changed by a soft reset. table 13. output mode control table 14. output format control address 0x74: output_mode_b address 0x75: config_status bit 6 dll range this bit sets the dll operating range to fast (tbd2msps to 250msps) or slow (40 to tbd1msps). the output_mode_b and config_status registers are used in conjunction to enable ddr mode and select the frequency range of the dll clock generator. the method of setting these options is different from the other registers. figure 45. setting output_mode_b register the procedure for setting output_mode_b is shown in figure 45. read the conten ts of output_mode_b and config_status and xor them. then xor this result with the desired value for output_mode_b and write that xor result to the register. dut test the kad2512 can produce preset or user defined patterns on the digital outputs to facilitate in-situ test- ing. a static word can be placed on the output bus, or two different words can alternate. in the alternate mode, the values defined as word 1 and word 2 (as shown in table 15) are set on the output bus on alter- nating clock phases. address 0xc0: test_io bits 7:6 user test mode these bits set the test mode to static (0x00) or alternate (0x01) mode. other values are re- served. the four lsbs in this register (output test mode) deter- mine the test pattern in combination with registers 0xc2 through 0xc5. refer to table 16. table 15. output test modes address 0xc2: user_patt1_lsb address 0xc3: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the first user-defined test word. address 0xc2: user_patt2_lsb address 0xc3: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the second user-defined test word. value 0x93[7:5] output mode 000 pin control 001 lvds 2ma 010 lvds 3ma 100 lvcmos value 0x93[2:0] output format 000 pin control 001 two?s complement 010 gray code 100 offset binary value 0xc0[3:0] output test mode 0000 off 0001 midscale 0010 positive full-scale 0011 negative full-scale 0100 checkerboard 0101 reserved 0110 reserved 0111 one/zero 1000 user pattern word 1 0x8000 0xffff 0x0000 0xaaaa n/a n/a 0xffff user_patt1 word 2 n/a n/a n/a 0x5555 n/a n/a 0x0000 user_patt2
KAD5512P-50 rev 0.5.1 preliminary page 24 spi memory map table 16. spi memory map addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value ( hex ) indexed/ global 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h g 01 reserved 02 burst_end 00h g 03-07 reserved 08 chip_id read only g 09 chip_version read only g 10 device_index_a adc01 adc00 00h i 11-1f reserved 20 offset_coarse cal. value i 21 offset_fine cal. value i 22 gain_coarse cal. value i 23 gain_medium cal. value i 24 g ain_fine cal. value i 25 modes 00h not affected by soft reset i 26-5f reserved 60-6f reserved 70 skew_diff 7fh g 71 phase_slip next clock edge 00h g 72 clock_divide 00h not affected by soft reset g 73 output_mode_a 00h not affected by soft reset g 74 output_mode_b dll range 0=fast 1=slow 00h not affected by soft reset g 75 config_status xor result read only g 76-bf reserved c1 reserved 00h g c2 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c3 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c4 user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h g c5 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h g c6-ff reserved reserved reserved reserved reserved reset pn short gen reserved coarse gain reserved reserved reserved chip id # chip version # differential skew output mode [2:0] 000=pin control 001=lvds 2ma 010=lvds 3ma 100=lvcmos other codes=reserved output format [2:0] 000=pin control 001=twos complement 010=gray code 100=offset binary other codes=reserved reserved g 00h test_io output test mode [3:0] 7=one/zero word toggle 8=user input 9-15=reserved 0=off 1=midscale short 2=+fs short 3= ? fs short 4=checker board 5=reserved 6=reserved dut test c0 reserved user test mode [2:0] 00=single 01=alternate 10=single once 11=alternate once reset pn long gen spi config dut info indexed dut config/control global dut config/control burst end address [7:0] clock divide [2:0] 000=pin control 001=divide by 1 010=divide by 2 100=divide by 4 other codes=reserved reserved medium gain fine offset coarse offset power down mode [2:0] 000=pin control 001=normal operation 010=nap 100=sleep other codes=reserved fine gain
KAD5512P-50 rev 0.5.1 preliminary page 25 equivalent circuits figure 46. analog inputs figure 47. clock inputs figure 48. tri-level digital inputs figure 49. digital inputs figure 50. lvds outputs figure 51. cmos outputs figure 52. vcm_out output layout considerations split ground and power planes data converters operating at high sampling frequen- cies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer in- puts for the analog input and clock signals. locate transformers and terminations as close to the chip as possible. avdd clkp clkn avdd avdd to charge pipeline 11k ? 11k ? avdd 18k ? 18k ?
KAD5512P-50 rev 0.5.1 preliminary page 26 exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. bypass and filtering bulk capacitors should have low equivalent series re- sistance. tantalum is a g ood choice. for best per- formance, keep ceramic bypass capacitors very close to device pins. longer traces will increase in- ductance, resulting in diminished dynamic perform- ance and accuracy. make sure that connections to ground are direct and low impedance. avoid form- ing ground loops. lvds outputs output traces and connections must be designed for 50 ? (100 ? differential) characteristic impedance. keep traces direct and minimize bends where possi- ble. avoid crossing ground and power plane breaks with signal traces. lvcmos outputs output traces and connections must be designed for 50 ? characteristic impedance. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) which will not be operated do not require connec- tion to ensure optimal adc performance. these in- puts can be left floating if they are not used. tri-level inputs (napslp, outmode, outfmt, clkdiv) accept a floating input as a valid state, and therefore should be biased according to th e desired functionality. definitions analog input bandwidth is the analog input fre- quency at which the spectral output power at the fundamental frequency (as determined by fft analy- sis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time re- quired after the rise of the clock input for the sam- pling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-distortion ratio (sinad). in db, it is calculated as: enob = (sinad-1.76) / 6.02 gain error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage (less 2 lsb). it is typically expressed in percent. integral non-linearity (inl) is the deviation of each individual code from a line drawn from negative full- scale (1/2 lsb below the first code transition) through positive full-scale (1/2 lsb above the last code transi- tion). the deviation of any given code from this line is measured from the center of that code. least significant bit (lsb) is the bit that has the small- est value or weight in a digital word. its value in terms of input voltage is v fs /(2 n -1) where n is the resolution in bits. missing codes are output codes that are skipped and will never appear at the adc output. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of a change in input voltage necessary to correct a change in output code that results from a change in power supply voltage. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the converter?s full-scale input power is used as the reference.
KAD5512P-50 rev 0.5.1 preliminary page 27 outline dimensions spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spuri- ous spectral component may or may not be a har- monic. two-tone sfdr is the ratio of the rms value of the lowest power input tone to the rms value of the peak spurious component, which may or may not be an imd product. figure 53. 72qfn dimensions
KAD5512P-50 rev 0.5.1 preliminary page 28 ordering guide the KAD5512P-50 is compliant with eu directive 2002 /95/ec regarding the restriction of hazardous sub- stances (rohs). contact kenet for a materials declaration for this product. revision history 14-may-07: rev 0.1 updated to new format 21-jun-07: rev 0.2 errata updated 13-aug-07: rev 0.3 content/specification updates 07-dec-07: rev 0.4 content/specification updates 21-feb-08: rev 0.5 updated specifications, added functional descriptions 19-mar-08 rev 0.5.1 corrected minor typos preliminary datasheet this datasheet contains preliminary technical data, which is subject to change without notice. contact kenet prior to initiating design activity using this product. model speed package temp. range KAD5512P-50q72 500msps 72-qfn -40c to +85c

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